1. Field of the Invention
The invention relates to processes for etching silicon and, more particularly, the invention relates to a method of etching polysilicon to form a storage node for an integrated circuit memory device.
2. Description of the Background Art
Trenches formed in semiconductor substrates have many uses in producing integrated circuits including isolation, capacitor formation, transistor formation, and the like. One important use of trenches is in the formation of a trench capacitor as a storage node for a dynamic random access memory (DRAM) device. Trench capacitors are desirable because they occupy a relatively small area, while having large electrode surface area due to the depth of the trench used to form the capacitor. In a conventional trench capacitor, the trench walls form one electrode of the capacitor, the walls are coated with a thin dielectric material and then the remaining trench is filled with polysilicon such that the polysilicon forms the second electrode of the capacitor. As such, trench-based DRAM devices utilize less area than other forms of memory devices that use planar or stacked capacitors. To maximize the capacitance of the trench capacitor, the surface area of the trench walls is maximized, i.e., the trench is deep and the walls are substantially vertical.
Another form of storage node is created by masking and etching a layer of polysilicon to create protrusions of polysilicon that rise from an oxide layer. The protrusions are isolated from one another by the supporting oxide layer. The polysilicon is then coated with a thin dielectric layer and an outer coating of polysilicon is applied to the dielectric layer such that the inner polysilicon protrusion and the outer polysilicon layer form the electrodes of the capacitor. This form of storage enables the surface of the inner polysilicon to be tailored to achieve a large surface area.
Traditionally, storage nodes are formed using an anisotropic chemical or reactive ion etching of a masked polysilicon substrate. Etching chemistries utilize combinations of such chemicals as HBr, Cl.sub.2, O.sub.2, SF.sub.6, and N.sub.2. The etch rate of polysilicon when exposed to combinations of such chemicals is approximately 4000 .ANG./min with a photoresist selectivity of less than 2:1, typically 1.8:1 is readily achievable. The maximum etch rate is directly proportional to the maximum achievable throughput for processing a wafer, i.e., the slower the etch rate, the less wafers are completely processed in a unit of time. As such, it is desirable to increase throughput of the process by increasing the etch rate. However, it is generally known that an increase in the etch rate decreases the etch selectivity. As such, for high etch rates a thick layer of photoresist (e.g., 8000 to 9000 .ANG.) is necessary. Such a thick photoresist causes incorrect etching of the storage node side walls resulting in anomalous sidewall definition and improper storage node operation.
Therefore, a need exists in the art for a polysilicon etching method that increases the etch rate without impacting photoresist selectivity.